1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and more particularly relates to a manufacturing method of a semiconductor device having a vertical transistor.
2. Description of the Related Art
Semiconductors, particularly memory devices have been reduced in chip size over the years for cost reductions. Accordingly, vertical transistors having a 4F2 structure (where F denotes a minimum feature size) have been adopted as cell transistors of a DRAM (Dynamic Random Access Memory). Conventional planar transistors are adopted as transistors of peripheral circuits as before because demand on peripheral circuits for size reduction is not so strong as compared with that on cell transistors. However, when cells and the peripheral circuits differ in a transistor structure, the number of processing steps greatly increases. Therefore, under these circumstances, it is recently considered to adopt vertical transistors as the transistors of the peripheral circuits (see Japanese Patent Application Laid-Open No. 2008-288391).
As described in the Japanese Patent Application Laid-Open No. 2008-288391, two proximate silicon pillars are employed in vertical transistors disposed in the peripheral circuits. One of the silicon pillars is used as a channel, impurity diffusion layers are provided in upper and lower portions of the silicon pillar, respectively, and a side surface thereof is covered with a gate electrode via a gate insulating film. The other silicon pillar is used as a dummy silicon pillar for laterally extending a length of the gate electrode and a gate contact plug is provided using an extension part.
The gate electrode is formed by forming a gate insulating film on the side surface of each of the silicon pillar and the dummy silicon pillar, then depositing a polycrystalline silicon film on an entire surface of a substrate by CVD (Chemical Vapor Deposition) method, and further performing etching-back. The film thickness of the gate electrode (a deposition amount of the polycrystalline silicon film) is set to be equal to or larger than half the length between the silicon pillar and the dummy silicon pillar. With this setting, the gate electrode formed on the silicon pillar is integrated with that formed on the dummy silicon pillar and then it is possible to control a channel within the silicon pillar via the gate contact plug.